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Allwinner /D1H /SMHC[0] /EMMC_DDR_SBIT_DET

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Interpret as EMMC_DDR_SBIT_DET

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (full)HALF_START_BIT 0 (disabled)HS400_MD_EN

HALF_START_BIT=full, HS400_MD_EN=disabled

Description

eMMC4.5 DDR Start Bit Detection Control Register

Fields

HALF_START_BIT

Control for start bit detection mechanism inside mstorage based on duration of start bit

0 (full): Full cycle

1 (less): Less than one full cycle
HS400_MD_EN

HS400 Mode Enable

0 (disabled): Disabled

1 (enabled): Enabled

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data